1. Field of the Invention
The present invention relates generally to an interposer configured to receive a semiconductor device for testing. More specifically, the invention pertains to such a test interposer having an alignment fence for receiving and aligning semiconductor devices, such as flip-chip type semiconductor dice, ball grid array (BGA) packages, and chip scale packages (CSPs), with test sockets of the interposer. The present invention also relates to methods for fabricating such a test interposer.
2. Background of Related Art
The semiconductor industry produces extremely large numbers of miniature electrical devices, or “chips” or dice, which are referred to as semiconductor devices. Semiconductor devices are installed in essentially every electronic device. Such devices are typically fabricated in large numbers on a wafer of semiconductive material (e.g., silicon, gallium arsenide, or indium phosphide). The individual chips or dice are then singulated from the wafer.
Tests are typically performed at several stages of manufacture for the purposes of evaluating the electrical characteristics of various circuits of the semiconductor devices and for detecting electrical, structural, and other types of faults in the semiconductor devices. These tests are sometimes performed on representative semiconductor devices and sometimes on each semiconductor device of a certain type, depending on the criticality of use, manufacturing costs, and expectation of flaws.
Conventionally, the semiconductor industry favored a “final” electrical testing of semiconductor devices, which was effected before semiconductor devices were packaged with electrical leads extending therefrom and encapsulated in a protective material. However, it is now recognized that conventional packaging processes may cause significant numbers of semiconductor devices to fail. For example, as a semiconductor device is being encapsulated, the protective material may cause particulate die coat penetration, “bond wire sweep,” which may break electrical connections made by the bond wires or cause electrical shorts between adjacent bond wires, and other problems. Accordingly, it is desirable to test semiconductor devices after they have been packaged.
Some state of the art semiconductor devices lack conventional packages (e.g., leads and encapsulants) or are minimally packaged. Flip-chip type semiconductor devices may be left unpackaged and connected directly to a higher level substrate by way of conductive structures, such as solder balls, disposed between the bond pads of the flip-chip and corresponding contact pads of the higher level substrate.
Ball grid array packages, a type of flip-chip semiconductor device, may include a semiconductor die disposed on and electrically connected to an interposer. The interposer has contact pads on the opposite side thereof that are arranged in a pattern complementary to that of contact pads on a higher level substrate to which the ball grid array package is to be connected. The interposer may also include electrical traces that lead to contact pads arranged in a different pattern than the bond pads of the semiconductor die and, therefore, reroute the bond pads of the semiconductor die.
Another type of state of the art package is the so-called “chip scale package,” wherein the dimensions of the total package are only slightly larger than the dimensions of the semiconductor die thereof. A chip scale package typically includes a flip-chip type semiconductor die with one or more thin layers of protective material (e.g., plastic encapsulant) on the active surface thereof. Conductive structures (e.g., solder bumps) protrude from bond pads of the flip-chip type semiconductor die and extend above the layer of protective material. Chip scale packages may also have one or more thin layers of protective material on the edges or backsides of the semiconductor dice thereof. Ball grid array packages may be formed as chip scale packages.
When these types of semiconductor devices are tested, the solder bumps or other conductive structures protruding therefrom may not properly align with the corresponding test sockets of a test substrate so as to establish adequate electrical contacts between the tested semiconductor device and the test substrate. Moreover, if misalignment occurs, the conductive structures may be damaged.
In order to reduce potential damage to conductive structures, such as solder bumps, during the testing of flip-chip type semiconductor devices, interposers have been used between a test substrate and a semiconductor device to be tested. These interposers may comprise micromachined silicon or ceramic structures that include metal-lined recesses for receiving conductive structures of a semiconductor device to be tested, metal-filled vias extending from the bottom of each recess to the opposite, bottom side of the interposer, and conductive structures, such as solder bumps, communicating with the metal-filled vias and protruding from the bottom side of the interposer. The recesses of the interposer are configured to receive the conductive structures of a semiconductor device to be tested without stressing or damaging the conductive structures. The metal lining of and metal-filled via communicating with each recess facilitates electrical communication between a conductive structure disposed in each recess and the corresponding, underlying conductive structure protruding from the bottom of the interposer. The conductive structures of the interposer are precisely aligned with test pads or sockets of a test substrate so as to establish an electrical connection between a semiconductor device assembled with the interposer and the test substrate. The test pads or sockets of the test substrate communicate with known semiconductor device test equipment.
Nonetheless, the conductive structures protruding from a semiconductor device to be tested may be damaged when assembled with such an interposer. Moreover, since the recesses of such interposers are configured to receive the conductive structures of a semiconductor device without stressing, deforming, or otherwise damaging the conductive structures, the interposer may fail to make adequate electrical connections between some of the conductive structures and their corresponding test pads or sockets of the test substrate. Moreover, test interposers typically lack any alignment component other than the recesses thereof.
Accordingly, it appears that the art is lacking a structure for aligning the conductive structures of a semiconductor device with corresponding test pads or sockets of a test substrate without stressing or damaging the conductive structures while facilitating adequate electrical connections between the conductive structures and the test pads or sockets.
In the past decade, a manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
Essentially, stereolithography as conventionally practiced involves the use of a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the at least partially consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which may be fixed and the minimum thickness of a layer which may be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which may not be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
However, to the inventors' knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required. Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assure precise, repeatable placement of components. In particular, stereolithography has not been employed to fabricate interposers for aligning and connecting a semiconductor device to a test substrate.